EP2AGX95EF29C6N Datasheet, PDF (137/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–29
Source-Synchronous Mode
If data and clock arrive at the same time on the input pins, the same phase
relationship is maintained at the clock and data ports of any IOE input register.
Figure 5–24 shows an example waveform of the clock and data in source-synchronous
mode. This mode is recommended for source-synchronous data transfers. Data and
clock signals at the IOE experience similar buffer delays as long as you use the same
I/O standard.
Figure 5–24. Phase Relationship Between Clock and Data in Source-Synchronous Mode in Arria II Devices
Data pin
PLL
reference clock
at input pin
Data at register
Clock at register
Source-synchronous mode compensates for the delay of the clock network used plus
any difference in the delay between these two paths:
■ Data pin-to-IOE register input
■ Clock input pin-to-the PLL PFD input
You can use the PLL Compensation assignment in the Quartus II software
Assignment Editor to select which input pins are used as the PLL compensation
targets. You can include your entire data bus, provided the input registers are clocked
by the same output of a source-synchronous compensated PLL. All input pins must
be on the same side of the device for the clock delay to be properly compensated. The
PLL compensates for the input pin with the longest pad-to-register delay among all
input pins in the compensated bus.
If you do not assign the PLL Compensation assignment, the Quartus II software
automatically selects all pins driven by the compensated output of the PLL as the
compensation target.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration