EP2AGX95EF29C6N Datasheet, PDF (67/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 3: Memory Blocks in Arria II Devices
Clocking Modes
3–19
Clocking Modes
Arria II memory blocks support the following clocking modes:
■ “Independent Clock Mode” on page 3–19
■ “Input and Output Clock Mode” on page 3–19
■ “Read and Write Clock Mode” on page 3–19
■ “Single Clock Mode” on page 3–20
c Violating the setup or hold time on the memory block address registers could corrupt
the memory contents. This applies to both read and write operations.
Table 3–9 lists the supported clocking mode/memory mode combinations.
Table 3–9. Internal Memory Clock Modes for Arria II Devices
Clocking Mode
Independent
Input and output
Read and write
Single clock
True Dual-Port Mode Simple Dual-Port Mode
v
—
v
v
—
v
v
v
Single-Port Mode
—
v
—
v
ROM Mode
v
v
—
v
FIFO Mode
—
—
v
v
Independent Clock Mode
Arria II memory blocks can implement independent clock mode for true dual-port
memories. In this mode, a separate clock is available for each port (clock A and
clock B). Clock A controls all registers on the port A side; clock B controls all registers
on the port B side. Each port also supports independent clock enables for both port A
and port B registers, respectively. Asynchronous clears are supported only for output
latches and output registers on both ports.
Input and Output Clock Mode
Arria II memory blocks can implement input and output clock mode for true and
simple dual-port memories. In this mode, an input clock controls all registers related
to the data input to the memory block including data, address, byte enables, read
enables, and write enables. An output clock controls the data output registers.
Asynchronous clears are available on output latches and output registers only.
Read and Write Clock Mode
Arria II memory blocks can implement read and write clock mode for simple
dual-port memories. In this mode, a write clock controls the data-input,
write-address, and write-enable registers. Similarly, a read clock controls the
data-output, read-address, and read-enable registers. The memory blocks support
independent clock enables for both the read and write clocks. Asynchronous clears
are available on data output latches and registers only.
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration