EP2AGX95EF29C6N Datasheet, PDF (62/380 Pages) Altera Corporation – Device Interfaces and Integration

3–14
Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Figure 3–13 shows timing waveforms for read and write operations in simple
dual-port mode with unregistered outputs for M9K and M144K blocks. Registering
the M9K and M144K block outputs delay the q output by one clock cycle.
Figure 3–13. Simple Dual-Port Timing Waveforms for M9K and M144K Blocks
wrclock
wren
wraddress an-1
an
a0
a1
a2
a3
data _din-1
din
rdclock
rden
rdaddress
bn
b0
b1
q (asynch) doutn-1
doutn
dout0
a4
a5
a6
din4
din5
din6
b2
b3
Figure 3–14 shows the timing waveforms for read and write operations in simple
dual-port mode with unregistered outputs in the MLAB. The write operation is
triggered by the falling clock edges.
Figure 3–14. Simple Dual-Port Timing Waveforms for MLABs
wrclock
wren
wraddress
data
rdclock
rden
rdaddress
q (asynch)
an-1
din-1
bn
doutn-1
an
a0
din
b0
doutn
a1
a2
a3
a4
a5
a6
din4
din5
din6
b1
dout0
b2
b3
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation