EP2AGX95EF29C6N Datasheet, PDF (68/380 Pages) Altera Corporation – Device Interfaces and Integration

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Chapter 3: Memory Blocks in Arria II Devices
Design Considerations
When using read and write clock mode, the output read data is unknown if you
perform a simultaneous read and write to the same address location. If you require
the output data to be a known value, use either single clock mode or input and output
clock mode, and choose the appropriate read-during-write behavior in the
MegaWizard Plug-In Manager.
Single Clock Mode
Arria II memory blocks can implement single clock mode for true dual-port, simple
dual-port, and single-port memories. In this mode, a single clock, together with a
clock enable, is used to control all registers of the memory block. Asynchronous clears
are available on output latches and output registers only.
Design Considerations
This section describes guidelines for designing with memory blocks.
Selecting Memory Block
The Quartus II software automatically partitions user-defined memory into
embedded memory blocks by taking into account both speed and size constraints
placed on your design. For example, the Quartus II software may spread out memory
across multiple memory blocks when resources are available to increase the
performance of your design. You can manually assign memory to a specific block size
using the RAM MegaWizard Plug-In Manager.
MLABs can implement single-port SRAM through emulation with the Quartus II
software. Emulation results in minimal additional logic resources used. Because of the
dual-purpose architecture of the MLAB, it only has data input registers and output
registers in the block. MLABs gain input address registers and additional optional
data output registers from adjacent ALMs with register packing.
f For more information about register packing, refer to the Logic Array Blocks and
Adaptive Logic Modules in Arria II Devices chapter.
Conflict Resolution
When using the memory blocks in true dual-port mode, it is possible to attempt two
write operations to the same memory location (address). Because there is no conflict
resolution circuitry built into the memory blocks, this results in unknown data being
written to that location. Therefore, you must implement conflict resolution logic,
external to the memory block, to avoid address conflicts.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation