EP2AGX95EF29C6N Datasheet, PDF (209/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 7: External Memory Interfaces in Arria II Devices
7–7
Memory Interfaces Pin Support for Arria II Devices
Table 7–3. Number of DQ/DQS Groups per Side in Arria II GZ Devices (Part 2 of 2)
Device
Package
Number of DQ/DQS Groups
Side
Refer to
×4 (1) ×8/×9
×16/×18 ×32/×36 (2)
EP2AGZ225
1517-pin
FineLine BGA
All sides
26
12
4
0
Figure 7–14 on
page 7–17
EP2AGZ300 1517-pin
Left/Right
26
12
4
EP2AGZ350
FineLine BGA _Top/Bottom
26
12
4
0
Figure 7–15 on
2 (3)
page 7–18
Notes to Table 7–3:
(1) Some of the ×4 groups may use R_UP and R_DN pins. You cannot use these groups if you use the Arria II GZ calibrated OCT feature.
(2) To interface with a ×36 QDR II+/QDR II SRAM device in a Arria II GZ FPGA that does not support the ×32/×36 DQ/DQS group, refer to
“Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface” on page 7–21.
(3) These ×32/×36 DQ/DQS groups have 40 pins instead of 48 pins per group. You cannot place BWSn pins within the same DQ/DQS group as the
write data pins because of insufficient pins available.
Figure 7–4 through Figure 7–10 show the maximum number of DQ/DQS groups per
side of the Arria II GX device. These figures represent the die-top view of the
Arria II GX device.
Figure 7–4 shows the number of DQ/DQS groups per bank in EP2AGX45 and
EP2AGX65 devices in the 358-pin Ultra FineLine BGA (UBGA) package.
Figure 7–4. Number of DQ/DQS Groups per Bank in EP2AGX45 and EP2AGX65 Devices in the 358-Pin Ultra Fineline BGA
Package (Note 1), (2)
I/O Bank 8A
22 User I/Os
×4=2
×8/×9=1
×16/×18=0
×32/×36=0
I/O Bank 7A
38 User I/Os
×4=4
×8/×9=2
×16/×18=1
×32/×36=0
EP2AGX45
and EP2AGX65 Devices in the
358-Pin Ultra FineLine BGA
I/O Bank 3A
22 User I/Os
×4=2
×8/×9=1
×16/×18=0
×32/×36=0
I/O Bank 4A
38 User I/Os
×4=4
×8/×9=2
×16/×18=1
×32/×36=0
I/O Bank 6A (3)
18 User I/Os
×4=2
×8/×9=1
×16/×18=0
×32/×36=0
I/O Bank 5A
18 User I/Os
×4=2
×8/×9=1
×16/×18=0
×32/×36=0
Notes to Figure 7–4:
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Arria II GX devices in the 358-pin UBGA package do not support the 36 QDR II+/QDR II SRAM interface.
(3) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a 4 DQ/DQS group with any of their pin members used for
configuration purposes. Ensure that the DQ/DQS groups you chose are not also used for configuration.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration