EP2AGX95EF29C6N Datasheet, PDF (148/380 Pages) Altera Corporation – Device Interfaces and Integration

5–40
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
When you use automatic switchover mode, the clkbad[0] and clkbad[1] signals
indicate the status of the two clock inputs. When they are asserted, the clock sense
block has detected that the corresponding clock input has stopped toggling. These
two signals are not valid if the frequency difference between inclk0 and inclk1 is
greater than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is
being selected as the reference clock to the PLL. When the frequency difference
between the two clock inputs is more than 20%, the activeclock signal is the only
valid status signal.
Figure 5–35 shows an example waveform of the switchover feature with automatic
switchover mode. In this example, the inclk0 signal is stuck low. After the inclk0
signal is stuck at low for approximately two clock cycles, the clock sense circuitry
drives the clkbad[0] signal high. Also, because the reference clock signal is not
toggling, the switchover state machine controls the multiplexer through the clksw
signal to switch to the backup clock, inclk1.
Figure 5–35. Automatic Switchover Upon Loss of Clock Detection for Arria II Devices
inclk0
inclk1
(1)
muxout
clkbad0
clkbad1
activeclock
Note to Figure 5–35:
(1) Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this figure, switchover is enabled on
the falling edge of inclk1.
Manual Override Mode
In automatic switchover with manual override mode, you can use the clkswitch
input for user- or system-controlled switch conditions. You can use this mode for
same-frequency switchover or to switch between inputs of different frequencies. For
example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control the
switchover when you use clkswitch because the automatic clock-sense circuitry
cannot monitor clock input (inclk0 and inclk1) frequencies with a frequency
difference of more than 100% (2x). This feature is useful when the clock sources
originate from multiple cards on the backplane, requiring a system-controlled
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation