EP2AGX95EF29C6N Datasheet, PDF (218/380 Pages) Altera Corporation – Device Interfaces and Integration

7–16
Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
Figure 7–13 shows the number of DQ/DQS groups per bank in Arria II GZ
EP2AGZ300 and EP2AGZ350 devices in the 1152-pin FineLine BGA package.
Figure 7–13. Number of DQ/DQS Groups per Bank in EP2AGZ300 and EP2AGZ350 Devices in the 1152-Pin FineLine BGA
Package (Note 1), (2), (3)
DLL0
I/O Bank 8A I/O Bank 8B
40 User I/Os 24 User I/Os
×4=6
×8/×9=3
×16/×18=1
×32/×36=1 (5)
×4=4
×8/×9=2
×16/×18=1
I/O Bank 8C
32 User I/Os
×4=3
×8/×9=1
×16/×18=0
I/O Bank 7C
32 User I/Os
×4=3
×8/×9=1
×16/×18=0
I/O Bank 7B I/O Bank 7A
24 User I/Os 40 User I/Os
×4=6
×4=4
×8/×9=2
×8/×9=3
×16/×18=1
×16/×18=1 _{×32/×36=1 (5)}
DLL3
I/O Bank 1A
48 User I/Os
×4=7
×8/×9=3
×16/×18=1
I/O Bank 1C
42 User I/Os
×4=6
×8/×9=3
×16/×18=1
EP2AGZ300 and EP2AGZ350 Devices
in the 1152-Pin FineLine BGA
I/O Bank 6A
48 User I/Os
×4=7
×8/×9=3
×16/×18=1
I/O Bank 6C
42 User I/Os
×4=6
×8/×9=3
×16/×18=1
DLL1
I/O Bank 3A I/O Bank 3B
40 User I/Os 24 User I/Os
×4=6
×4=4
×8/×9=3
×8/×9=2
×16/×18=1 ×16/×18=1
×32/×36=1 (5)
I/O Bank 3C
32 User I/Os
×4=3
×8/×9=1
×16/×18=0
I/O Bank 4C
32 User I/Os
×4=3
×8/×9=1
×16/×18=0
I/O Bank 4B ^{I/O Bank 4A}
24 User I/Os ^{40 User I/Os}
×4=4
×4=6
×8/×9=2
×8/×9=3
×16/×18=1 ×16/×18=1
×32/×36=1 (5)
DLL2
Notes to Figure 7–13:
(1) You can also use DQS/DQSn pins in some of the ×4 groups as R_UP and R_DN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as R_UP and R_DN pins for OCT calibration. If two pins of a ×4 group are used as R_UP and R_DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(2) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(3) You can also use some of the DQ/DQS pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQ/DQS group with any of its pin members
used for configuration purposes. Ensure that the DQ/DQS groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQ/DQS groups, depending on your configuration scheme.
(4) These ×32/×36 DQ/DQS groups have 40 pins instead of 48 pins per group.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011 Altera Corporation