EP2AGX95EF29C6N Datasheet, PDF (81/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 4: DSP Blocks in Arria II Devices
4–5
Simplified DSP Operation
Equation 4–3. Four-Multiplier Adder Equation (44-Bit Accumulation)
W_n[43..0] = W_n-1[43..0] ± Z_n[37..0]
In these equations, n denotes sample time and P[36..0] are the results from the
two-multiplier adder units.
Equation 4–2 provides a sum of four 18 × 18-bit multiplication operations
(four-multiplier adder), and Equation 4–3 provides a four 18 × 18-bit multiplication
operation, but with a maximum of a 44-bit accumulation capability by feeding the
output from the output register bank back to the adder/accumulator block, as shown
in Figure 4–3.
You can bypass all register stages depending on which mode you select, except
accumulation and loopback mode. In these two modes, you must enable at least one
set of the registers. If the register is not enabled, an infinite loop occurs.
Figure 4–3. Four-Multiplier Adder and Accumulation Capability
Input ¹⁴⁴
Data
44
Result[]
Half-DSP Block
To support FIR-like structures efficiently, a major addition to the DSP block in Arria II
devices is the ability to propagate the result of one half block to the next half block
completely in the DSP block without additional soft logic overhead. This is achieved
by the inclusion of a dedicated addition unit and routing that adds the 44-bit result of
a previous half block with the 44-bit result of the current block. The 44-bit result is
either fed to the next half block or out of the DSP block with the output register stage
shown in Figure 4–4. Detailed examples are described in later sections.
December 2010 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration