EP2AGX95EF29C6N Datasheet, PDF (96/380 Pages) Altera Corporation – Device Interfaces and Integration

4–20
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
Two-Multiplier Adder Sum Mode
In the two-multiplier adder configuration, the DSP block can implement four 18-bit
two-multiplier adders (2 two-multiplier adders per half-DSP block). You can
configure the adders to take the sum or difference of two multiplier outputs.
Summation or subtraction must be selected at compile time. The two-multiplier adder
function is useful for applications such as FFTs, complex FIR, and IIR filters.
Figure 4–13 shows the DSP block configured in the two-multiplier adder mode.
Figure 4–13. Two-Multiplier Adder Mode Shown for Half-DSP Block (Note 1)
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
output_round
output_saturate
overflow (2)
dataa_0[17..0]
datab_0[17..0]
+
dataa_1[17..0]
result[ ]
datab_1[17..0]
Half-DSP Block
Notes to Figure 4–13:
(1) In a half-DSP block, you can implement 2 two-multiplier adders.
(2) Block output for accumulator overflow and saturate overflow.
The loopback mode is a sub-feature of the two-multiplier adder mode. Figure 4–14
shows the DSP block configured in the loopback mode. This mode takes the 36-bit
summation result of the two multipliers and feeds back the most significant 18-bits to
the input. The lower 18-bits are discarded. You have the option to disable or zero-out
the loopback data with the dynamic zero_loopback signal. A logic 1 value on the
zero_loopback signal selects the zeroed data or disables the looped back data, and a
logic 0 selects the looped back data.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation