EP2AGX95EF29C6N Datasheet, PDF (93/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
4–17
36-Bit Multiplier
You can construct a 36 × 36 multiplier with four 18 × 18 multipliers. This
simplification fits into one half-DSP block and is implemented in the DSP block
automatically by selecting 36 × 36 mode. Arria II devices can have up to two 36-bit
multipliers per DSP block (one 36-bit multiplier per half DSP block). The 36-bit
multiplier is also under the independent multiplier mode but uses the entire half-DSP
block, including the dedicated hardware logic after the pipeline registers to
implement the 36 × 36-bit multiplication operation, as shown in Figure 4–10.
The 36-bit multiplier is useful for applications requiring more than 18-bit precision;
for example, for the mantissa multiplication portion of single precision and extended
single precision floating-point arithmetic applications.
Figure 4–10. 36-Bit Independent Multiplier Mode Shown for Half-DSP Block
clock[3..0]
ena[3..0]
aclr[3..0]
signa
signb
dataa_0[35..18]
datab_0[35..18]
dataa_0[17..0]
datab_0[35..18]
dataa_0[35..18]
datab_0[17..0]
dataa_0[17..0]
datab_0[17..0]
+
72
+
result[ ]
+
Half-DSP Block
Double Multiplier
You can configure the Arria II DSP block to support an unsigned 54 × 54-bit multiplier
that is required to compute the mantissa portion of an IEEE double precision floating
point multiplication. You can build a 54 × 54-bit multiplier with basic 18 × 18
multipliers, shifters, and adders. To efficiently use built-in shifters and adders in the
Arria II DSP block, a special double mode (partial 54 × 54 multiplier) is available that
December 2010 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration