EP2AGX95EF29C6N Datasheet, PDF (369/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 11: JTAG Boundary-Scan Testing in Arria II Devices
BST Operation Control
11–3
Figure 11–2 shows the Arria II GX HSSI receiver/input clock buffer BSC.
Figure 11–2. HSSI Receiver/Input Clock Buffer BSC with IEEE Std. 1149.6 BST Circuitry for Arria II GX Devices
BSCAN
PMA
SDOUT
0
DQ
1
0
DQ
1
BSRX1
BSOUT1
BSRX0
BSOUT0
Hysteretic
Memory
AC JTAG Test
Receiver
Mission
(DATAIN)
Optional INTEST/RUNBIST
not supported
Pad
Rx Input
Buffer
Pad
Hysteretic
Memory
AC JTAG Test
Receiver
HIGHZ SDIN SHIFT CLK
UPDATE
AC_TEST MEM_INIT
MODE
AC_MODE
Capture
Update
Registers
BST Operation Control
Table 11–1 lists the boundary-scan register length for Arria II devices.
Table 11–1. Boundary-Scan Register Length for Arria II Devices
Device
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGZ225
EP2AGZ300
EP2AGZ350
Boundary-Scan Register Length
1,227
1,227
1,467
1,467
1,971
1,971
2,274
2,682
2,682
December 2013 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration