EP2AGX95EF29C6N Datasheet, PDF (185/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 6: I/O Features in Arria II Devices
OCT Support
6–21
Table 6–11 lists the I/O standards that support R_S OCT with and without calibration.
Table 6–11. R_S OCT Selectable I/O Standards With and Without Calibration for Arria II Devices
I/O Standard
R_S OCT Termination Setting
Row I/O ()
Column I/O ()
50
50
3.3-V LVTTL/LVCMOS (1), (2)
25
25
50
50
3.0-V LVTTL/LVCMOS
25
25
50
50
2.5-V LVTTL/LVCMOS
25
25
50
50
1.8-V LVTTL/LVCMOS
25
25
1.5-V LVCMOS
50
50
25 (3)
25
1.2-V LVCMOS
50
50
25 (3)
25
SSTL-2 Class I
50
50
SSTL-2 Class II
25
25
SSTL-18 Class I
50
50
SSTL-18 Class II
25
25
SSTL-15 Class I
50
50
SSTL-15 Class II (2)
—
25
HSTL-18 Class I
50
50
HSTL-18 Class II
25
25
HSTL-15 Class I
50
50
HSTL-15 Class II
25 (3)
25
HSTL-12 Class I
50
50
HSTL-12 Class II
25 (3)
25
Notes to Table 6–11:
(1) The 3.3-V LVTTL/LVCMOS standard is supported using V_CCIO at 3.0 V.
(2) Applicable for Arria II GZ devices only.
(3) Applicable for Arria II GX devices only.
Left-Shift R_S OCT Control for Arria II GZ Devices
Arria II GZ devices support left-shift series termination control. You can use left-shift
series termination control to get the calibrated R_S OCT with half of the impedance
value of the external reference resistors connected to the RUP and RDN pins. This feature
is useful in applications that require both 25- and 50- calibrated R_S OCT at the
same V_CCIO. For example, if your application requires 25- and 50- calibrated
R_S OCT for SSTL-2 Class I and Class II I/O standards, you only need one OCT
calibration block with 50- external reference resistors.
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration