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EP2AGX95EF29C6N Datasheet, PDF (213/380 Pages) Altera Corporation – Device Interfaces and Integration | |||
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Chapter 7: External Memory Interfaces in Arria II Devices
Memory Interfaces Pin Support for Arria II Devices
7â11
Figure 7â8 shows the number of DQ/DQS groups per bank in Arria II GX EP2AGX95,
EP2AGX125, EP2AGX190, and EP2AGX260 devices in the 780-pin FineLine BGA
package.
Figure 7â8. Number of DQ/DQS Groups per Bank in EP2AGX95, EP2AGX125, EP2AGX190 and EP2AGX260 Devices in the
780-Pin FineLine BGA Package (Note 1)
I/O Bank 8A
58 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 7A
70 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
EP2AGX95, EP2AGX125, EP2AGX190,
and EP2AGX260 Devices
in the 780-Pin FineLine BGA
I/O Bank 6A (2)
50 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 5A
66 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
I/O Bank 3A
54 User I/Os
Ã4=6
Ã8/Ã9=3
Ã16/Ã18=1
Ã32/Ã36=0
I/O Bank 4A
74 User I/Os
Ã4=8
Ã8/Ã9=4
Ã16/Ã18=2
Ã32/Ã36=1
Notes to Figure 7â8:
(1) All I/O pin counts include 12 dedicated clock inputs (CLK4 to CLK15) that you can use for data inputs.
(2) Several configuration pins in Bank 6A are shared with DQ/DQS pins. You cannot use a ï´4 DQ/DQS group with any of their pin members used for
configuration purposes. Ensure that the DQ/DQS groups you chose are not also used for configuration.
June 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration
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