EP2AGX95EF29C6N Datasheet, PDF (355/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Document Revision History
9–69
Document Revision History
Table 9–28 lists the revision history for this chapter.
Table 9–28. Document Revision History
Date
July 2012
December 2011
June 2011
December 2010
July 2010
November 2009
June 2009
February 2009
Version
4.3
4.2
4.1
4.0
3.0
2.0
1.1
1.0
Changes Made
■ Updated “FPP Configuration Using a MAX II Device as an External Host” section.
■ Added pull-up resistor to nCONFIG in Figure 9–1, Figure 9–2, Figure 9–3,
Figure 9–10, Figure 9–11, and Figure 9–12.
■ Updated Table 9–8, Table 9–9, Table 9–10, and Table 9–12.
■ Updated Figure 9–16 and Figure 9–17.
■ Updated “Configuration” and “FPP Configuration Using a MAX II Device as an
External Host” sections.
■ Minor text edits.
■ Updated Table 9–9, Table 9–10, Table 9–12, Table 9–18, and Table 9–23.
■ Updated the “Programming Serial Configuration Devices” and “Configuration Data
Decompression” sections.
■ Removed references to the “ByteBlaster MV” and “MasterBlaster” cables as they are
discontinued.
■ Minor text edits.
■ Updated for the Quartus II software version 10.1 release.
■ Added Arria II GZ devices information.
■ Minor text edits.
Updated for Arria II GX v10.0 release:
■ Updated Table 9–9 and Table 9–17.
■ Updated Figure 9–4, Figure 9–5, Figure 9–13, Figure 9–16, Figure 9–17,
Figure 9–21, and Figure 9–30.
■ Updated “AS and Fast AS Configuration (Serial Configuration Devices)” and “Flexible
Security Key Storage” sections.
■ Added “Guidelines for Connecting Serial Configuration Device to Arria II Devices on
an Active Serial Interface” section.
■ Minor text edits.
Updated for Arria II GX v9.1 release:
■ Updated Table 9–3, Table 9–10, Table 9–11, Table 9–13.
■ Updated Figure 9–2, Figure 9–3, and Figure 9–6.
■ Updated “VCCPD Pins”, “JTAG Configuration”, “Remote System Upgrade Mode”,
“Remote System Upgrade State Machine”, “User Watchdog Timer” sections.
■ Minor text edits.
■ Updated Table 9–2, Table 9–3, Table 9–9, Table 9–10, Table 9–19, and Table 9–21.
■ Updated Figure 9–6, Figure 9–11, and Figure 9–16.
■ Updated “VCCIO Pins for I/O Banks 3C and 8C”, “FPP Configuration Using an
External Host”, and “Programming Serial Configuration Devices” sections.
■ Removed “Volatite or Non-Volatile Key with JTAG Anti-Tamper Protection Bit Set”
section.
Initial release.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration