EP2AGX95EF29C6N Datasheet, PDF (363/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 10: SEU Mitigation in Arria II Devices
Error Detection Timing
10–7
Table 10–5 lists the registers shown in Figure 10–1.
Table 10–5. Error Detection Registers for Arria II Devices
Register
Description
Syndrome Register
This register contains the CRC signature of the current frame through the error detection
verification cycle. The CRC_ERROR signal is derived from the contents of this register.
Error Message
Register
This 46-bit register contains information on the error type, location of the error, and the actual
syndrome. The types of errors and location reported are single- and double-adjacent bit errors.
The location bits for other types of errors are not identified by the EMR. The content of the register
is shifted out through the SHIFT_EDERROR_REG JTAG instruction or to the core through the core
interface.
JTAG Update Register
This register is automatically updated with the contents of the EMR one cycle after the 46-bit
register content is validated. It includes a clock enable, which must be asserted prior to being
sampled into the JTAG shift register. This requirement ensures that the JTAG Update Register is
not being written into by the contents of the EMR at the same time that the JTAG shift register is
reading its contents.
User Update Register
This register is automatically updated with the contents of the EMR one cycle after the 46-bit
register content is validated. It includes a clock enable, which must be asserted prior to being
sampled into the user shift register. This requirement ensures that the user update register is not
being written into by the contents of the EMR at the same time that the user shift register is
reading its contents.
JTAG Shift Register
This register is accessible by the JTAG interface and allows the contents of the JTAG update
register to be sampled and read out by SHIFT_EDERROR_REG JTAG instruction.
User Shift Register
This register is accessible by the core logic and allows the contents of the user update register to
be sampled and read by user logic.
JTAG Fault Injection
Register
This 21-bit register is fully controlled by the EDERROR_INJECT JTAG instruction. This register
holds the information of the error injection that you want in the bitstream.
Fault Injection Register
The content of the JTAG fault injection register is loaded into this 21-bit register when it is
updated.
Error Detection Timing
When you enable the error detection CRC feature through the Quartus II software, the
device automatically activates the CRC error detection process after entering user
mode, after configuration, and after initialization is complete.
If an error is detected within a frame, CRC_ERROR is driven high at the end of the error
location search, after the EMR is updated. At the end of this cycle, the CRC_ERROR pin is
pulled low for a minimum of 32 clock cycles. If the next frame contains an error,
CRC_ERROR is driven high again after the EMR is overwritten by the new value. You
can start to unload the error message on each rising edge of the CRC_ERROR pin. Error
detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator with a divisor
that sets the maximum frequency. Table 10–6 lists the minimum and maximum error
detection frequencies for Arria II devices.
Table 10–6. Minimum and Maximum Error Detection Frequencies for Arria II Devices
Device Type
Arria II
Error Detection
Frequency
100 MHz / 2ⁿ
Maximum Error
Detection Frequency
50 MHz
Minimum Error Detection
Frequency
390 kHz
Valid Divisors (n)
1, 2, 3, 4, 5, 6, 7, 8
February 2014 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration