EP2AGX95EF29C6N Datasheet, PDF (132/380 Pages) Altera Corporation – Device Interfaces and Integration

5–24
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–21 shows the clock I/O pins associated with Arria II GX PLLs.
Figure 5–21. External Clock Outputs for Arria II GX PLLs
Internal Logic
C0
C1
C2
Arria II GX
C3
PLLs
C4
C5
C6
m
clkena0 (3)
clkena1 (3)
PLL<#>_CLKOUT<#>p (1), (2)
PLL<#>_CLKOUT<#>n (1), (2)
Notes to Figure 5–21:
(1) You can feed these clock output pins with any one of the C[6..0],or m counters.
(2) The PLL<#>_CLKOUT<#>p and PLL<#>_CLKOUT<#>n pins can be either single-ended or pseudo-differential clock outputs. The Arria II GX PLL
only routes single-ended I/Os to PLL<#>CLKOUT<#>p pins, while you can use PLL<#>_CLKOUT<#>n pins as user I/Os.
(3) These external clock enable signals are available only when you use the ALTCLKCTRL megafunction.
For Arria II GX devices, any of the output counters (C[6..0]) or the M counter can feed
the dedicated external clock outputs, as shown in Figure 5–21. Therefore, one counter
or frequency can drive all the output pins available from a given PLL.
For Arria II GZ devices, each top and bottom PLL supports six clock I/O pins,
organized as three pairs of pins:
■ 1st pair—two single-ended I/O or one differential I/O
■ 2nd pair—two single-ended I/O or one differential external feedback input
(FBp/FBn)
■ 3rd pair—two single-ended I/O or one differential input
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation