EP2AGX95EF29C6N Datasheet, PDF (175/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 6: I/O Features in Arria II Devices
I/O Structure
6–11
I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output enable
path for handling the OE signal to the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. You can
bypass each block of the output and output enable paths. Figure 6–3 and Figure 6–4
show the Arria II IOE structure.
Figure 6–3. IOE Structure for Arria II GX Devices
OE Register
OE
from
D ^PRN Q
Core
Write
Data
form
Core
To
Core
To
Core
Read
Data
to
Core
DQS
CQn
clkin
OE Register
PRN
DQ
Output Register
D ^PRN Q
Output Register
D ^PRN Q
Output Enable
Pin Delay
VCCIO
PCI Clamp
VCCIO
Programmable
Current
Strength and
Slew Rate
Control
Output Pin
Delay
Output Buffer
Open Drain
Input Pin Delay
to Input Register
Input Buffer
Programmable
Pull-Up Resistor
From OCT
Calobration
Block
On-Chip
Termination
Bus-Hold
Circuit
Input Pin Delay
to internal Cells
Input Register
PRN
DQ
Synchronization
Registers
DQS Bus
to
Input Register Delay
Input Register
D ^PRN Q
Input Register
PRN
D
Q
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration