EP2AGX95EF29C6N Datasheet, PDF (155/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–47
Scan Chain Description
Arria II GX PLLs have a 180-bit scan chain. Table 5–15 lists the number of bits for each
component of an Arria II GX PLL.
Table 5–15. PLL Reprogramming Bits for Arria II GX Devices
Block Name
Number of Bits
Counter
Other (1)
Total
C6 (2)
16
2
18
C5
16
2
18
C4
16
2
18
C3
16
2
18
C2
16
2
18
C1
16
2
18
C0
16
2
18
M
16
2
18
N
16
2
18
Charge Pump Current
0
3
3
VCO Post-Scale divider (K)
1
0
1
Loop Filter Capacitor (3)
0
2
2
Loop Filter Resistor
0
5
5
Unused CP/LF
0
7
7
Total number of bits
—
—
180
Notes to Table 5–15:
(1) Includes two control bits: rbypass for bypassing the counter and rselodd to select the output clock duty cycle.
(2) The LSB for C6 low-count value is the first bit shifted into the scan chain.
(3) The MSB for loop filter is the last bit shifted into the scan chain.
The length of the scan chain varies for different Arria II GZ PLLs. The top and bottom
PLLs have ten post-scale counters and a 234-bit scan chain, while the left and right
PLLs have seven post-scale counters and a 180-bit scan chain.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration