EP2AGX95EF29C6N Datasheet, PDF (364/380 Pages) Altera Corporation – Device Interfaces and Integration

10–8
Chapter 10: SEU Mitigation in Arria II Devices
Error Detection Timing
You can set a lower clock frequency by specifying a division factor in the Quartus II
software (refer to “Software Support” on page 10–9). The divisor is a power of two (2),
where n is between 1 and 8. The divisor ranges from 2 through 256 (refer to
Equation 10–1).
Equation 10–1.
error detection frequency
=
-¹--⁰---⁰----^M-----^H------^z-
2ⁿ
1 The error detection frequency reflects the frequency of the error detection
process for a frame because the CRC calculation in Arria II devices is done
on a per-frame basis.
The EMR is updated whenever an error occurs. If the error location and message are
not shifted out before the next error location is found, the previous error location and
message are overwritten by the new information. To avoid this, you must shift these
bits out within one frame CRC verification. The minimum interval time between each
update for the EMR depends on the device and the error detection clock frequency.
However, slowing down the error detection clock frequency slows down the error
recovery time for the SEU event.
Table 10–7 lists the estimated minimum interval time between each update for the
EMR in Arria II devices.
Table 10–7. Minimum Update Interval for Error Message Register in Arria II Devices
Device
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGZ225
EP2AGZ300
EP2AGZ350
Timing Interval (s)
11.04
11.04
14.88
14.88
19.64
19.64
19.8
21.8
21.8
The CRC calculation time for the error detection circuitry to check from the first until
the last frame depends on the device and the error detection clock frequency.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
February 2014 Altera Corporation