EP2AGX95EF29C6N Datasheet, PDF (28/380 Pages) Altera Corporation – Device Interfaces and Integration

1–14
Chapter 1: Overview for the Arria II Device Family
Reference and Ordering Information
Reference and Ordering Information
Figure 1–3 shows the ordering codes for Arria II devices.
Figure 1–3. Packaging Ordering Information for Arria II Devices
EP2AGX 45 C F 17
C
4
N
Family Signature
EP2AGX
EP2AGZ
Device Density
GX: 45, 65, 95, 125, 190,260
GZ: 225, 300, 350
Transceiver Count
C: 4
D: 8
E: 12
F:16
H: 24
Package Type
F: FineLine BGA (FBGA)
U: Ultra FineLine BGA (UBGA)
H: Hybrid FineLine BGA (HBGA)
Ball Array Dimension
Corresponds to pin count
17 = 358 pins
25 = 572 pins
29 = 780 pins
35 = 1152 pins
40 = 1517 pins
Optional Suffix
Indicates specific device options
ES: Engineering sample
N: Lead-free devices
Speed Grade
3, 4, 5, or 6, with 3 being the fastest
Operating Temperature
C: Commercial temperature (tJ = 0°C to 85°C)
I: Industrial temperature (tJ = -40°C to 100°C)
Document Revision History
Table 1–10 lists the revision history for this chapter.
Table 1–10. Document Revision History (Part 1 of 2)
Date
July 2012
December 2011
June 2011
June 2011
December 2010
Version
Changes
4.4
Replaced Table 1-10. External Memory Interface Maximum Performance for Arria II Devices
with link to the External Memory Interface Spec Estimator online tool.
4.3 Updated Table 1–4 and Table 1–9.
4.2 Updated Table 1–2.
■ Updated Figure 1–2.
■ Updated Table 1–10.
4.1 ■ Updated the “Arria II Device Feature” section.
■ Added Table 1–6.
■ Minor text edits.
■ Updated for the Quartus II software version 10.0 release
■ Added information about Arria II GZ devices
■ Updated Table 1–1, Table 1–4, Table 1–5, Table 1–6, Table 1–7, and Table 1–9
4.0 ■ Added Table 1–3
■ Added Figure 1–2
■ Updated Figure 1–3
■ Updated “Arria II Device Feature” and “Arria II Device Architecture” section
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation