EP2AGX95EF29C6N Datasheet, PDF (27/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 1: Overview for the Arria II Device Family
Arria II Device Architecture
1–13
■ Remote System Upgrade
■ Allows error-free deployment of system upgrades from a remote location
securely and reliably without an external controller
■ Soft logic (either the Nios II embedded processor or user logic) implementation
in the device helps download a new configuration image from a remote
location, store it in configuration memory, and direct the dedicated remote
system upgrade circuitry to start a reconfiguration cycle
■ Dedicated circuitry in the remote system upgrade helps to avoid system down
time by performing error detection during and after the configuration process,
recover from an error condition by reverting back to a safe configuration
image, and provides error status information
SEU Mitigation
■ Offers built-in error detection circuitry to detect data corruption due to soft errors
in the configuration random access memory (CRAM) cells
■ Allows all CRAM contents to be read and verified to match a
configuration-computed cyclic redundancy check (CRC) value
■ You can identify and read out the bit location and the type of soft error through the
JTAG or the core interface
JTAG Boundary Scan Testing
■ Supports JTAG IEEE Std. 1149.1 and IEEE Std. 1149.6 specifications
■ IEEE Std. 1149.6 supports high-speed serial interface (HSSI) transceivers and
performs boundary scan on alternating current (AC)-coupled transceiver channels
■ Boundary-scan test (BST) architecture offers the capability to test pin connections
without using physical test probes and capture functional data while a device is
operating normally
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration