EP2AGX95EF29C6N Datasheet, PDF (264/380 Pages) Altera Corporation – Device Interfaces and Integration

8–18
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
DPA Mode
In DPA mode, the DPA circuitry automatically chooses the optimal phase between the
source-synchronous reference clock and the input serial data to compensate for the
skew between the two signals. The reference clock must be a differential signal.
Figure 8–14 shows the DPA mode datapath. Use the DPA_diffioclk clock to write
serial data into the synchronizer. Use the LVDS_diffioclk clock to read the serial data
from the synchronizer. Use the same LVDS_diffioclk clock in the data realignment
and deserializer blocks.
Figure 8–14. Receiver Datapath in DPA Mode (Note 1), (2), (3)
rx_out
10
IOE Supports SDR, DDR, or Non-Registered Datapath
2
IOE
FPGA
Fabric
rx_divfwdclk
rx_outclock
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
2
(LOAD_EN, diffioclk)
diffioclk
Clock
Multiplier
LVDS Receiver
+
rx_in
Synchronizer
DOUT DIN
DPA Circuitry
Retimed
Data
DIN
DPA Clock
(DPA_LOAD_EN,
3 _{DPA_diffioclk,}
rx_divfwdclk)
3
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
PLL (4)
rx_inclock
Notes to Figure 8–14:
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
8 Serial LVDS
Clock Phases
LVDS Clock Domain
DPA Clock Domain
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation