EP2AGX95EF29C6N Datasheet, PDF (78/380 Pages) Altera Corporation – Device Interfaces and Integration

4–2
Chapter 4: DSP Blocks in Arria II Devices
DSP Block Overview
DSP Block Overview
Arria II GX devices have two to four columns of DSP blocks, while Arria II GZ
devices have two to seven columns of DSP blocks. These DSP blocks implement
multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift
functions. Architectural highlights of the Arria II DSP block include:
■ High-performance, power-optimized, fully registered, and pipelined
multiplication operations
■ Natively supported 9-bit, 12-bit, 18-bit, and 36-bit word lengths
■ Natively supported 18-bit complex multiplications
■ Efficiently supported floating-point arithmetic formats (24 bits for single precision
and 53 bits for double precision)
■ Signed and unsigned input support
■ Built-in addition, subtraction, and accumulation units to efficiently combine
multiplication results
■ Cascading 18-bit input bus to form tap-delay line for filtering applications
■ Cascading 44-bit output bus to propagate output results from one block to the next
block without external logic support
■ Rich and flexible arithmetic rounding and saturation units
■ Efficient barrel shifter support
■ Loopback capability to support adaptive filtering
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010 Altera Corporation