EP2AGX95EF29C6N Datasheet, PDF (269/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Source-Synchronous Timing Budget
8–23
Source-Synchronous Timing Budget
This section describes the timing budget, waveforms, and specifications for
source-synchronous signaling in Arria II devices. Timing analysis for the differential
block is different from traditional synchronous timing analysis techniques. Therefore,
it is important to understand how to analyze timing for high-speed differential
signals. This section defines the source-synchronous differential data orientation
timing parameters, timing budget definitions, and how to use these timing
parameters to determine your design’s maximum performance.
Differential Data Orientation
There is a set relationship between an external clock and the incoming data. For
operation at 1 Gbps and a serialization factor of 10, the external clock is multiplied
by 10. You can set the phase-alignment in the PLL to coincide with the sampling
window of each data bit. The data is sampled on the falling edge of the multiplied
clock.
Figure 8–20 shows the data bit orientation of x10 mode.
Figure 8–20. Bit Orientation
inclock/outclock
data in
MSB
10 LVDS Bits
LSB
9 87 6543210
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at high
frequencies. Figure 8–21 shows data bit orientation for a channel operation. These
figures are based on the following:
■ serialization factor equals clock multiplication factor
■ edge alignment is selected for phase alignment
■ implemented in hard SERDES
For other serialization factors, use the Quartus II software tools to find the bit position
in the word. The bit positions after deserialization are listed in Table 8–8.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration