EP2AGX95EF29C6N Datasheet, PDF (305/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
AS and Fast AS Configuration (Serial Configuration Devices)
9–19
AS and Fast AS Configuration (Serial Configuration Devices)
Arria II GX and GZ devices are configured using a serial configuration device in the
AS configuration scheme and the fast AS configuration scheme, respectively. These
configuration devices are low-cost devices with non-volatile memory that feature a
simple four-pin interface and a small form factor. These features make serial
configuration devices an ideal low-cost configuration solution.
f For more information about serial configuration devices, refer to the Serial
Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet
chapter in volume 2 of the Configuration Handbook.
Serial configuration devices provide a serial interface to access configuration data.
During device configuration, Arria II devices read configuration data using the serial
interface, decompress data if necessary, and configure their SRAM cells. This scheme
is referred to as the AS configuration scheme because the Arria II device controls the
configuration interface. This scheme contrasts with the PS configuration scheme,
where the configuration device controls the interface.
1 The Arria II decompression and design security features are available when
configuring your Arria II GX device using AS mode and when configuring your
Arria II GZ device using fast AS mode.
Serial configuration devices have a four-pin interface—serial clock input (DCLK), serial
data output (DATA), AS data input (ASDI), and an active-low chip select (nCS). This
four-pin interface connects to the Arria II device pins, as shown in Figure 9–6.
Figure 9–6. Single Device AS Configuration
V_CCIO/V_CCPGM V_CCIO/V_CCPGM V_CCIO/V_CCPGM
(1)
(1)
(1)
Serial Configuration
Device
10 kΩ 10 kΩ 10 kΩ
Arria II Device
nSTATUS
CONF_DONE nCEO
N.C.
nCONFIG
nCE
DATA
DCLK
nCS
ASDI
GND
DATA0
DCLK
nCSO
CLKUSR
(3)
ASDO
MSEL [n..0]
(4)
(2)
Notes to Figure 9–6:
(1) Connect the pull-up resistors to the V_CCIO power supply of bank 3C for Arria II GX devices and to V_CCPGM at a 3.0-V
power supply for Arria II GZ devices.
(2) Arria II devices use the ASDO-to-ASDI path to control the configuration device.
(3) Arria II devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
(4) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for
an Arria II GX device, refer to Table 9–6 on page 9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
Table 9–7 on page 9–10.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration