EP2AGX95EF29C6N Datasheet, PDF (203/380 Pages) Altera Corporation – Device Interfaces and Integration

June 2011
AIIGX51007-4.1
AIIGX51007-4.1
7. External Memory Interfaces in Arria II
Devices
This chapter describes the hardware features in Arria^® II devices that facilitate
high-speed memory interfacing for the double data rate (DDR) memory standard
including delay-locked loops (DLLs). Memory interfaces also use I/O features such as
on-chip termination (OCT), programmable input delay chains, programmable output
delay, slew rate adjustment, and programmable drive strength.
Arria II devices provide an efficient architecture to quickly and easily fit wide external
memory interfaces with their small modular I/O bank structure. The I/Os are
designed to provide flexible and high-performance support for existing and emerging
external DDR memory standards, such as DDR3, DDR2, DDR SDRAM, QDR II,
QDR II+ SRAM, and RLDRAM II. The Arria II FPGA supports DDR external memory
on the top, bottom, left, and right I/O banks.
The high-performance memory interface solution includes the self-calibrating
ALTMEMPHY megafunction and UniPHY Intellectual Property (IP) core, optimized
to take advantage of the Arria II I/O structure and the Quartus^® II TimeQuest Timing
Analyzer. The ALTMEMPHY megafunction and UniPHY IP core provide the total
solution for the highest reliable frequency of operation across process, voltage, and
temperature (PVT) variations.
The ALTMEMPHY megafunction and UniPHY IP core instantiate a phase-locked loop
(PLL) and PLL reconfiguration logic to adjust the resynchronization phase shift based
on PVT variation.
This chapter includes the following sections:
■ “Memory Interfaces Pin Support for Arria II Devices” on page 7–3
■ “Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface”
on page 7–21
■ “Arria II External Memory Interface Features” on page 7–24
1 Arria II GZ devices only support the UniPHY IP core. Arria II GX devices support the
QDR II and QDR II + SRAM controller with the UniPHY IP core, and DDR3, DDR2,
and the DDR SDRAM controller with the ALTMEMPHY megafunction.
1 RLDRAM II is only available in Arria II GZ devices.
f For more information about any of the above-mentioned features, refer to the I/O
Features in Arria II Devices or the Clock Networks and PLLs in Arria II Devices chapter.
f
For more information about external memory system specifications, implementation,
board guidelines, timing analysis, simulation, debug information, ALTMEMPHY
megafunction and UniPHY IP core support for Arria II devices, refer to the External
Memory Interface Handbook.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
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Arria II Device Handbook Volume 1: Device Interfaces and Integration
June 2011
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