EP2AGX95EF29C6N Datasheet, PDF (105/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
4–29
Two saturation modes are supported in Arria II devices:
■ Asymmetric saturation mode
■ Symmetric saturation mode
You must select one of the two options at compile time.
In 2’s complement format, the maximum negative number that can be represented is
–2 ^(n-1), and the maximum positive number is 2^(n-1) – 1. Symmetrical saturation limits
the maximum negative number to –2^(n-1) + 1. For example, for 32 bits:
■ Asymmetric 32-bit saturation: Max = 0×7FFFFFFF, Min = 0×80000000
■ Symmetric 32-bit saturation: Max = 0×7FFFFFFF, Min = 0×80000001
Table 4–8 lists how the saturation works. In this example, a 44-bit input is saturated to
36-bits.
Table 4–8. Examples of Saturation
44 to 36 Bits Saturation
Symmetric SAT Result
5926AC01342h
ADA38D2210h
7FFFFFFFFh
800000001h
Asymmetric SAT Result
7FFFFFFFFh
800000000h
Arria II devices have up to 16 configurable bit positions out of the 44-bit bus ([43:0])
for the rounding and saturate logic unit, providing higher flexibility. You must select
the 16 configurable bit positions at compile time. These 16-bit positions are located at
bits [21:6] for rounding and [43:28] for saturation, as shown in Figure 4–20.
Figure 4–20. Rounding and Saturation Locations
16 User defined SAT Positions (bit 43-28)
43 42
29 28
16 User defined RND Positions (bit 21-6)
10
43 42
21 20
76
0
1 For symmetric saturation, the RND bit position is to determine where the LSP for the
saturated data is located.
You can use the rounding and saturation function as described in regular supported
multiplication operations shown in Table 4–2 on page 4–7. However, for accumulation
type operations, the following convention is used.
The functionality of the rounding logic unit is in the format of:
Result = RND[∑(A × B)], when used for an accumulation type of operation.
Likewise, the functionality of the saturation logic unit is in the format of:
Result = SAT[∑(A × B)], when used for an accumulation type of operation.
December 2010 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration