EP2AGX95EF29C6N Datasheet, PDF (73/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 3: Memory Blocks in Arria II Devices
Design Considerations
3–25
Figure 3–26 shows a sample functional waveform of mixed-port read-during-write
behavior in old data mode.
Figure 3–26. M9K and M144K Mixed Port Read During Write: Old Data Mode
clk_a&b
wrena
address_a
data_a
byteena
rdenb
address_b
q_b_(asynch)
AAAA
11
A0
BBBB
01
CCCC
10
DDDD
A1
EEEE
11
FFFF
A0
A0 (old data) AAAA
AABB
A1
A1(old data) DDDD
EEEE
Figure 3–27 shows a sample functional waveform of mixed-port read-during-write
behavior for don’t care mode in M9K and M144K blocks.
Figure 3–27. M9K and M144K Mixed-Port Read-During-Write: Don’t Care Mode
clk_a&b
wrena
address_a
data_a
byteena
rdenb
address_b
q_b_(asynch)
AAAA
11
A0
BBBB
01
CCCC
10
DDDD
A1
EEEE
11
FFFF
A0
A1
XXXX (unknown data)
Mixed-port read-during-write is not supported when two different clocks are used in
a dual-port RAM. The output value is unknown during a dual-clock mixed-port
read-during-write operation.
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration