EP2AGX95EF29C6N Datasheet, PDF (51/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 3: Memory Blocks in Arria II Devices
3–3
Memory Features
Table 3–1. Summary of Memory Features in Arria II Devices (Part 2 of 2)
Feature
Mixed-port read-during-write
MLABs
Arria II GX Arria II GZ
Outputs set to old data,
new data, or
don’t care
M9K Blocks
Arria II GX Arria II GZ
Outputs set to old data or
don’t care
ECC Support
Soft IP support using the
Quartus II software
Soft IP support using the
Quartus II software
M144K Blocks
Arria II GZ
Outputs set to
old data or
don’t care
Built-in support in
×64-wide simple dual-port
mode or soft IP support
using the Quartus II
software
Table 3–2 lists the capacity and distribution of the memory blocks in each Arria II
device.
Table 3–2. Memory Capacity and Distribution in Arria II Devices
Device
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGZ225
EP2AGZ300
EP2AGZ350
MLABs
903
1,265
1,874
2,482
3,806
5,130
4,480
5,960
6,970
M9K Blocks
319
495
612
730
840
950
1,235
1,248
1,248
M144K
—
—
—
—
—
—
—
24
36
Total RAM Bits (including MLABs) (Kbits)
3,435
5,246
6,679
8,121
9,939
11,756
13,915
18,413
20,772
Memory Block Types
M9K and M144K memory blocks are dedicated resources. MLABs are dual-purpose
blocks. You can configure the MLABs as regular logic array blocks (LABs) or as
MLABs. Ten ALMs make up one MLAB. You can configure each ALM in an MLAB as
either a 64 × 1 or a 32 × 2 block, resulting in a 64 × 10 or 32 × 20 simple dual-port
SRAM block in a single MLAB.
Parity Bit Support
All memory blocks have built-in parity bit support. The ninth bit associated with each
byte can store a parity bit or serve as an additional data bit. No parity function is
actually performed on the ninth bit.
Byte Enable Support
All memory blocks support byte enables that mask the input data so that only specific
bytes of data are written. The unwritten bytes retain the previous written value. The
write enable (wren) signals, along with the byte enable (byteena) signals, control the
write operations of the RAM blocks.
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration