EP2AGX95EF29C6N Datasheet, PDF (131/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
5–23
PLL Hardware Overview in Arria II Devices
Figure 5–20 shows a simplified block diagram of the major components of the
Arria II PLL.
Figure 5–20. PLL Block Diagram for Arria II Devices
To DPA block on
Left/Right PLLs
pfdena
Dedicated
4
clock inputs
GCLK/RCLK
Cascade input
from adjacent PLL
inclk0
inclk1
Clock
Switchover
Block
÷n
clkswitch
clkbad0
clkbad1
activeclock
Lock
Circuit
locked
PFD
8
÷2
CP
LF
VCO
(2)
/2, /4
÷C0
8
÷C1
8
÷C2
÷C3
(1)
÷Cn
÷m
no compensation mode
ZDB, External feedback modes
LVDS Compensation mode
Source Synchronous, normal modes
Notes to Figure 5–20:
(1) The number of post-scale counters is seven for left and right PLLs and ten for top and bottom PLLs.
(2) This is the VCO post-scale counter K.
(3) The FBOUT port is fed by the M counter in Arria II PLLs. The FBOUT port is only available in Arria II GZ devices.
Casade output
to adjacent PLL
GCLKs
RCLKs
External clock
outputs
DIFFIOCLK from
Left/Right PLLs
LOAD_EN from
Left/Right PLLs
FBOUT (3)
External
memory
interface DLL
FBIN
DIFFIOCLK network
GCLK/RCLK network
1 You can drive the GCLK or RCLK clock input with an output from another PLL, a
pin-driven GCLK or RCLK, or through a clock control block, provided the clock
control block is fed by an output from another PLL, or a pin driven dedicated GCLK
or RCLK. An internally-generated global signal or general purpose I/O (GPIO) pin
cannot drive the PLL.
PLL Clock I/O Pins
For Arria II GX devices, each PLL supports one of the following clock I/O pin
configurations:
■ One single-ended I/O or one differential I/O pair.
■ Three single-ended I/O or three differential I/O pairs (this is only supported in
PLL_1 and PLL_3 of EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260
devices). You can only access one differential I/O pair or one single-ended pin at a
time.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration