EP2AGX95EF29C6N Datasheet, PDF (123/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
5–15
Table 5–11. RCLK Outputs From the PLL Clock Outputs for Arria II GZ Device (Part 2 of 2)
Clock Resource
RCLK[32..43]
RCLK[44..63]
PLL Number
L2
L3
B1
B2
R2
R3
T1
T2
—
—
—
—
v
v
—
—
—
—
—
—
—
—
v
v
Clock Control Block
Every GCLK and RCLK network has its own clock control block. The control block
provides the following features:
■ Clock source selection (dynamic selection for GCLKs)
■ GCLK multiplexing
■ Clock power down (static or dynamic clock enable or disable)
Figure 5–12 shows the GCLK select blocks for Arria II devices.
Figure 5–12. GCLK Control Block for Arria II Devices
CLK
Pin
PLL Counter 2
2
Outputs (3)
2
CLKSELECT[1..0]
(1)
Inter-Transceiver
Block Clock Lines
CLK
(4)
Pin
Internal
Logic
This multiplexer
supports user-controllable
dynamic switching
Static Clock
Select (2)
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 5–12:
(1) You can only dynamically control these clock select signals through internal logic when the device is operating in user
mode.
(2) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically
controlled during user mode operation.
(3) The left side of the Arria II GX device only allows PLL counter outputs as the dynamic clock source selection to the
GCLK network.
(4) This is only available on the left side of the Arria II GX device.
Select the clock source for the GCLK control block either statically with a setting in the
Quartus II software or dynamically with an internal logic to drive the multiplexer
select inputs. When selecting the clock source dynamically, you can either select two
PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration