EP2AGX95EF29C6N Datasheet, PDF (162/380 Pages) Altera Corporation – Device Interfaces and Integration

5–54
Chapter 5: Clock Networks and PLLs in Arria II Devices
Document Revision History
PLL Specifications
f For more information about PLL timing specifications, refer to the Device Datasheet for
Arria II Devices.
Document Revision History
Table 5–23 lists the revision history for this chapter.
Table 5–23. Document Revision History
Date
July 2012
June 2011
December 2010
July 2010
November 2009
June 2009
February 2009
Version
Changes
4.2 Updated “Periphery Clock Networks” section.
■ Updated Table 5–15.
■ Updated Figure 5–44.
4.1 ■ Updated “Dynamic Phase-Shifting” section.
■ Added Figure 5–5, Figure 5–6, Figure 5–7, and Figure 5–8.
■ Minor text edits.
■ Updated for the Quartus II software version 10.1 release.
■ Added Arria II GZ devices information.
■ Updated Table 5–1, Table 5–12, Table 5–20, and Table 5–21.
■ Added Figure 5–2, Figure 5–3, Figure 5–4, Figure 5–5, Figure 5–7, Figure 5–15,
4.0
Figure 5–11, Figure 5–16, Figure 5–18, Figure 5–19, Figure 5–24, Figure 5–26,
Figure 5–27, Figure 5–38, and Figure 5–39.
■ Added Table 5–5, Table 5–7, Table 5–9, Table 5–11, andTable 5–16.
■ Added “Clock Sources Per Quadrant” and “External Feedback Mode” sections.
■ Minor text edit.
Updated for Arria II GX v10.0 release:
■ Updated “Clock Regions” and “Arria II PLL Hardware Overview” sections.
3.0 ■ Updated Figure 5–44.
■ Removed sub-regional clock references.
■ Minor text edit.
Updated for Arria II GX v9.1 release:
■ Updated Table 5–1.
2.0 ■ Updated Figure 5–14.
■ Updated the “Periphery Clock (PCLK) Networks” and “Cascading PLLs” sections.
■ Minor text edit.
■ Updated Table 5–8.
1.1 ^{■ Updated Figure 5–13 and Figure 5–14.}
■ Updated the “PLL Clock I/O Pins” and “PLL Reconfiguration Hardware Implementation”
sections.
1.0 Initial release
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation