EP2AGX95EF29C6N Datasheet, PDF (361/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 10: SEU Mitigation in Arria II Devices
Error Detection Pin Description
10–5
Error Detection Pin Description
Table 10–3 lists the CRC_ERROR pin description for Arria II devices.
Table 10–3. CRC_ERROR Pin Description for Arria II Devices
Pin Name
CRC_ERROR
Pin Type
Description
I/O or
output
open-drain
Active high signal indicating that the error detection circuit has detected errors in the
configuration RAM bits. This is an optional pin and is used when you enable the error
detection CRC circuit. When you disable the error detection CRC circuit, it is a user I/O pin.
When using the WYSIWYG function, the CRC error output is a dedicated path to the
CRC_ERROR pin.
To use the CRC_ERROR pin, you can tie this pin to V_CCIO through a 10-k resistor.
Alternatively, depending on the input voltage specification of the system receiving the
signal, tie this pin to a different pull-up voltage.
Error Detection Block
The error detection block contains the logic necessary to calculate the 16-bit error
detection CRC signature for the configuration RAM bits in the Arria II device.
The CRC circuit continues running even if an error occurs. When a CRC error occurs,
the device sets the CRC_ERROR pin high. Table 10–4 lists the two types of CRC detection
that check the configuration bits for Arria II devices.
Table 10–4. Two Types of CRC Detection for Arria II Devices
User Mode CRC Detection
Configuration CRC Detection
■ This is the configuration RAM error checking ability
(16-bit error detection CRC) during user mode for use
by the CRC_ERROR pin.
■ For each frame of data, the pre-calculated 16-bit error
detection CRC enters the CRC circuit at the end of the
frame data and determines whether there is an error or
not.
■ If an error occurs, the search engine finds the location
of the error.
■ The error messages can be shifted out through the
JTAG instruction or core interface logics while the
error detection block continues running.
■ The JTAG interface reads out the 16-bit error detection
CRC result for the first frame and also shifts the 16-bit
error detection CRC bits to the 16-bit error detection
CRC storage registers for test purposes.
■ This is the 16-bit configuration CRC that is embedded in
every configuration data frame.
■ During configuration, after a frame of data is loaded into the
Arria II device, the pre-computed configuration CRC is
shifted into the CRC circuitry.
■ At the same time, the configuration CRC value for the data
frame shifted-in is calculated. If the pre-computed
configuration CRC and calculated configuration CRC values
do not match, nSTATUS is set low. Every data frame has a
16-bit configuration CRC; therefore, there are many 16-bit
configuration CRC values for the whole configuration
bitstream as there are many data frames. Every device has
different lengths of the configuration data frame.
■ You can deliberately introduce single error, double
errors, or double-adjacent errors to the configuration
memory for testing and design verification.
1 The “Error Detection Block” section focuses on the first type, the 16-bit CRC only,
when the device is in user mode.
February 2014 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration