EP2AGX95EF29C6N Datasheet, PDF (121/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
5–13
Table 5–5. Clock Input Pin Connectivity to the RCLK Networks for Arria II GZ Devices (Part 2 of 2)
Clock Resource
CLK (p/n Pins)
0 1 2 3 4 5 6 7 8 9 10 11 12
RCLK [45, 49, 53, 55, _{— — — — — — — — — — — — —}
59, 63]
RCLK [44, 48, 52, 54, _{— — — — — — — — — — — — —}
58, 62]
13 14 15
—v—
——v
Clock Input Connections to PLLs
Table 5–6 and Table 5–7 list dedicated clock input pin connectivity to Arria II PLLs.
Table 5–6. PLLs and PLL Clock Pin Drivers for Arria II GX Devices (Note 1)
PLL Number
Dedicated Clock Input Pin CLK (p/n Pins)
1
2
3
4
5
6
CLK[4..7]
—
—
v
v
—
—
CLK[8..11]
—
v
v
—
v
v
CLK[12..15]
v
v
—
—
—
—
Note to Table 5–6:
(1) PLL_5 and PLL_6 are connected directly to CLK[8..11]. PLL_1, PLL_2, PLL_3 and PLL_4 are driven by the clock input pins through a 4:1
multiplexer.
Table 5–7. PLLs and PLL Clock Pin Drivers for Arria II GZ Devices (Note 1), (2)
Dedicated Clock Input Pin CLK
(p/n Pins)
PLL Number
L2
L3
B1
B2
R2
R3
T1
T2
CLK[0..3]
v
v—
—
—
—
—
—
CLK[4..7]
—
—
v
v
—
—
—
—
CLK[8..11]
—
—
—
—
v
v
—
—
CLK[12..15]
—
—
—
—
—
—
v
v
Notes to Table 5–7:
(1) For single-ended clock inputs, only the CLK<#>p pin has a dedicated connection to the PLL. If you use the CLK<#>n pin, a GCLK is used.
(2) For the availability of the clock input pins in each device density, refer to the “Arria II Device Pin-Out Files” section of the Pin-Out Files for Altera
Devices.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration