EP2AGX95EF29C6N Datasheet, PDF (320/380 Pages) Altera Corporation – Device Interfaces and Integration

9–34
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
JTAG Configuration
Table 9–13. JTAG Pins Signals (Part 2 of 2)
Pin
Name
Pin Type
Description
Input pin that provides the control signal to determine the transitions of the TAP controller state
TMS
Test mode
select
machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set up TMS before the
rising edge of TCK. Transitions within the state machine occur on the falling edge of TCK after the
signal is applied to TMS. If the JTAG interface is not required on your board, you can disable the
JTAG circuitry by connecting this pin to logic high.
TCK
Test clock
input
Clock input to the BST circuitry. Some operations occur at the rising edge, while others occur at
the falling edge. If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting TCK to GND.
TRST
(1)
Test reset
input
(optional)
Active-low input to asynchronously reset the boundary-scan circuit. The TRST pin is optional
according to the IEEE Std. 1149.1 standard. If the JTAG interface is not required on your board,
you can disable the JTAG circuitry by connecting the TRST pin to GND. One k pull-up resistor to
V_CCPD if you do not use the TRST pin.
Note to Table 9–13:
(1) The TRST pin is only available for Arria II GZ devices.
During JTAG configuration, you can download data to the device on the PCB through
the USB-Blaster, ByteBlaster II, EthernetBlaster, or EthernetBlaster II download cable.
Figure 9–16 shows the JTAG configuration of a single Arria II device.
Figure 9–16. JTAG Configuration of a Single Device Using a Download Cable
V_CCIO/V_CCPGM
(1)
V_CCIO/V_CCPGM
(1)
10 kΩ
10 kΩ
GND ^N.C.
V_CCIO/V_CCPD
(2)
(3) _VCCIO/VCCPD
(2)
Arria II Device
(3)
nCE (4)
nCE0
TCK
TDO
TMS
nSTATUS
TDI
CONF_DONE
(5)
nCONFIG
(5)
MSEL[n..0]
(5)
DCLK
Download Cable
10-Pin Male Header
(JTAG Mode)
(Top View)
Pin 1
V_CCIO/V_CCPD
(2)
GND
V_IO (6)
1 kΩ
GND
GND
Notes to Figure 9–16:
(1) Connect the pull-up resistors to the V_CCIO power supply of I/O bank 3C for Arria II GX devices and to V_CCPGM (1.8-V, 2.5-V or 3.0-V) power supply
for Arria II GZ devices.
(2) Connect the pull-up resistor to the same supply voltage, V_CCIO for Arria II GX devices or V_CCPD for Arria II GZ devices as the USB-Blaster,
ByteBlaster II, EthernetBlaster, or EthernetBlaster II cable.
(3) The resistor value can vary from 1 K to 10 K.
(4) You must connect nCE to GND or drive it low for successful JTAG configuration.
(5) Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use the JTAG configuration, connect nCONFIG to
V_CCIO for Arria II GX device, V_CCPGM for Arria II GZ device, and MSEL to GND. Pull DCLK either high or low, whichever is convenient on your board.
(6) In the USB-Blaster and ByteBlaster II cables, this pin is a no connect.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation