EP2AGX95EF29C6N Datasheet, PDF (326/380 Pages) Altera Corporation – Device Interfaces and Integration

9–40
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Device Configuration Pins
Table 9–16 lists the dedicated configuration pins. You must connect these pins
properly on your board for successful configuration. Some of these pins may not be
required for your configuration schemes.
Table 9–16. Dedicated Configuration Pins on the Arria II Device (Part 1 of 4)
Pin Name
VCCPD
nIO_PULLUP
MSEL[2..0]
MSEL[3..0]
nCONFIG
User Mode
Configuration
Scheme
N/A
All
N/A
All
N/A
All
N/A
All
N/A
All
Pin Type
Power (1)
Input
Input
Input
Input
Description
Dedicated power pin. Use this pin to power the I/O
pre-drivers, the HSTL/SSTL input buffers, and the
MSEL[3..0] pins.
You must connect V_CCPD according to the I/O standard used
in the same bank:
■ For 3.3-V I/O standards, connect V_CCPD to 3.3 V
■ For 3.0-V I/O standards, connect V_CCPD to 3.0 V
■ For 2.5-V and below I/O standards, connect V_CCPD to 2.5 V
V_CCPD must ramp up from 0 V to 2.5, 3.0, or 3.3 V in 100 ms
(for standard POR) or 4 ms (for fast POR). If V_CCPD is not
ramped up in this specified time, your Arria II device is not
successfully configured.
Dedicated input that chooses whether the internal pull-up
resistors on the user I/O pins and dual-purpose I/O pins
(DATA[7..0], CLKUSR, INIT_DONE, DEV_OE, and
DEV_CLRn) are on or off before and during configuration. A
logic high turns off the weak internal pull-up resistors; a
logic low turns them on.
The nIO-PULLUP input buffer is powered by V_CC and has an
internal 5-k pull-down resistor that is always active. You
can tie the nIO-PULLUP directly to the V_CCPGM power supply
for Arria II GZ devices and the V_CCIO power supply for
Arria II GX devices, or GND.
Three-bit configuration input that sets the Arria II GZ device
configuration scheme. For more information about the
appropriate connections, refer to Table 9–7 on page 9–10.
You must hardwire these pins to V_CCPGM or GND.
The MSEL[2..0] pins have internal 5-k pull-down
resistors that are always active.
Four-bit configuration input that sets the Arria II GX device
configuration scheme. For more information about the
appropriate connections, refer to Table 9–6 on page 9–9.
You must hardwire these pins to V_CCPD or GND.
The MSEL[3..0] pins have internal 5-k pull-down
resistors that are always active.
Configuration control input. Pulling this pin low during
user-mode causes the device to lose its configuration data,
enter a reset state, and tri-state all I/O pins. Returning this
pin to a logic-high level starts a reconfiguration.
Configuration is possible only if this pin is high, except in
JTAG programming mode, when nCONFIG is ignored.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation