EP2AGX95EF29C6N Datasheet, PDF (174/380 Pages) Altera Corporation – Device Interfaces and Integration

6–10
Chapter 6: I/O Features in Arria II Devices
I/O Structure
Table 6–6. Pin Migration Across Densities in Arria II GZ Devices (Note 1) (Part 2 of 2)
Package
Pin Type
EP2AGZ225
Device
EP2AGZ300
EP2AGZ350
I/O
726
726
726
1517-pin
Clock
8
8
8
Flip Chip FBGA
XVCR channel
24
24
24
Note to Table 6–6:
(1) Each transceiver channel consists of two Tx pins, two Rx pins and a transceiver clock pin.
I/O Structure
The I/O element (IOE) in the Arria II devices contains a bidirectional I/O buffer and
I/O registers to support a completely embedded bidirectional single data rate (SDR)
or double data rate (DDR) transfer. The IOEs are located in I/O blocks around the
periphery of the Arria II device. There are up to four IOEs per row I/O block and four
IOEs per column I/O block. The row IOEs drive row, column, or direct link
interconnects. The column IOEs drive column interconnects.
The Arria II bidirectional IOE supports the following features:
■ Programmable input delay
■ Programmable output-current strength
■ Programmable slew rate
■ Programmable bus-hold
■ Programmable pull-up resistor
■ Programmable output delay
■ Open-drain output
■ R_S OCT
■ R_D OCT
■ R_T OCT for Arria II GZ devices
■ Dynamic OCT for Arria II GZ devices
■ PCI clamping diode
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation