EP2AGX95EF29C6N Datasheet, PDF (138/380 Pages) Altera Corporation – Device Interfaces and Integration

5–30
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Source-Synchronous Mode for LVDS Compensation
The goal of source-synchronous mode for LVDS compensation is to maintain the same
data and clock timing relationship seen at the pins at the internal
serializer/deserializer (SERDES) capture register, except that the clock is inverted
(180° phase shift), as shown in Figure 5–25. Thus, this mode ideally compensates for
the delay of the LVDS clock network plus any difference in the delay between these
two paths:
■ Data pin-to-SERDES capture register
■ Clock input pin-to-SERDES capture register. In addition, the output counter must
provide the 180° phase shift.
Figure 5–25. Source-Synchronous Mode for LVDS Compensation for Arria II Devices
Data pin
PLL
reference clock
at input pin
Data at register
Clock at register
No-Compensation Mode
In no-compensation mode, the PLL does not compensate for the clock networks. This
mode provides better jitter performance because the clock feedback into the PFD
passes through less circuitry. Both the PLL internal and external clock outputs are
phase-shifted with respect to the PLL clock input. Figure 5–26 shows an example
waveform of the PLL clocks’ phase relationship in no-compensation mode.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation