EP2AGX95EF29C6N Datasheet, PDF (315/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
PS Configuration
9–29
PS Configuration Timing
Figure 9–13 shows the timing waveform for a PS configuration when using a MAX II
device or microprocessor as an external host.
Figure 9–13. PS Configuration Timing Waveform (Note 1)
nCONFIG
t_CF2ST1
t_CFG
t_CF2CK
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA
User I/O
t_STATUS
t_CF2ST0
t_CLK
t_CF2CD
t_CH t_CL
t_ST2CK
t_DH
Bit 0 Bit 1
t_DSU
Bit 2
Bit 3
High-Z
(4)
Bit n
(5)
(6)
User Mode
INIT_DONE
t_CD2UM
Notes to Figure 9–13:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When
nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power-up, the Arria II device holds nSTATUS low for the time of the POR delay.
(3) After power-up, before and during configuration, CONF_DONE is low.
(4) Two DCLK falling edges are required after CONF_DONE goes high to begin initialization of the device.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) For Arria II GX devices, DATA[0]is a dedicated pin that is used for both PS and AS configuration modes and is not available as a user I/O pin after
configuration. For Arria II GZ devices, DATA[0] is available as a user I/O pin after configuration.
Table 9–12 lists the timing parameters for Arria II devices for PS configuration.
Table 9–12. PS Timing Parameters for Arria II Devices (Part 1 of 2)
Symbol
t_CF2CD
t_CF2ST0
t_CFG
t_STATUS
t_CF2ST1
(1)
t_CF2CK
t_ST2CK
t_DSU
t_DH
t_CH
t_CL
t_CLK
Parameter
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
nCONFIG low pulse width
nSTATUS low pulse width
nCONFIG high to nSTATUS high
nCONFIG high to first rising edge on DCLK
nSTATUS high to first rising edge of DCLK
Data setup time before rising edge on DCLK
Data hold time after rising edge on DCLK
DCLK high time
DCLK low time
DCLK period
Minimum
—
—
2
10
—
500
2
4
0
3.2
3.2
8
Maximum
800
800 (2)
—
500 (2)
500 (2)
—
—
—
—
—
—
—
Units
ns
ns
s
s
s
s
s
ns
ns
ns
ns
ns
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration