EP2AGX95EF29C6N Datasheet, PDF (261/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
Differential Receiver
8–15
Figure 8–11 shows a preset value of 4-bit times before rollover occurs. The rx_cda_max
signal pulses for one rx_outclock cycle to indicate that rollover has occurred.
Figure 8–11. Receiver Data Re-Alignment Rollover
rx_inclock
rx_channel_data_align
rx_outclock
rx_cda_max
Deserializer
The deserializer, which includes shift registers and parallel load registers, converts the
serial data from the bit slip to parallel data before sending the data to the FPGA fabric.
The deserialization factor supported is 4, 6, 7, 8, or 10. You can bypass the deserializer
to support DDR (x2) and SDR (x1) operations, as shown in Figure 8–12. You cannot
use the DPA and data realignment circuit when the deserializer is bypassed. The IOE
contains two data input registers that can operate in DDR or SDR mode.
Figure 8–12. Deserializer Bypass (Note 1), (2), (3)
2
rx_out
FPGA
Fabric
rx_divfwdclk
rx_outclock
IOE Supports SDR, DDR, or Non-Registered Datapath
2
IOE
Deserializer
DOUT DIN
Bit Slip
DOUT DIN
2
(LOAD_EN, diffioclk)
diffioclk
Clock
Multiplexer
LVDS Receiver
+
rx_in
Synchronizer
DOUT DIN
DPA Circuitry
Retimed ^DIN
Data
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
3 ^{(LVDS_LOAD_EN,}
LVDS_diffioclk,
rx_outclk)
PLL (4)
8 Serial LVDS
Clock Phases
Notes to Figure 8–12:
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(4) Arria II GX center/corner PLL or Arria II GZ left/right PLL.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration