EP2AGX95EF29C6N Datasheet, PDF (65/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
3–17
Figure 3–17 shows true dual-port timing waveforms for the write operation at port A
and the read operation at port B with the read-during-write behavior set to new data.
Registering the RAM outputs delay the q outputs by one clock cycle.
Figure 3–17. True Dual-Port Timing Waveform
clk_a
wren_a
address_a
data_a
q_a (asynch)
clk_b
wren_b
address_b
q_b (asynch)
an-1
din-1
an
din
din-1
a0
din
a1
dout0
a2
dout1
a3
dout2
a4
din4
dout3
a5
din5
din4
a6
din6
din5
bn
doutn-1
b0
doutn
b1
dout0
b2
dout1
b3
dout2
Shift-Register Mode
All Arria II memory blocks support shift register mode. Embedded memory block
configurations can implement shift registers for digital signal processing (DSP)
applications, such as finite impulse response (FIR) filters, pseudo-random number
generators, multi-channel filtering, and auto- and cross-correlation functions. These
and other DSP applications require local data storage, traditionally implemented with
standard flipflops that quickly exhaust many logic cells for large shift registers. A
more efficient alternative is to use embedded memory as a shift-register block, which
saves logic cell and routing resources.
The size of a shift register (w × m × n) is determined by the input data width (w), the
length of the taps (m), and the number of taps (n). You can cascade memory blocks to
implement larger shift registers.
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration