EP2AGX95EF29C6N Datasheet, PDF (114/380 Pages) Altera Corporation – Device Interfaces and Integration

5–6
Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Periphery Clock Networks
PCLK networks are a collection of individual clock networks driven from the
periphery of the Arria II device. Clock outputs from the DPA block, PLD-transceiver
interface clocks, I/O pins, and internal logic can drive the PCLK networks. Figure 5–5
through Figure 5–8 show CLK pins and PLLs that can drive PCLK networks in
Arria II devices.
The number of PCLKs for each Arria II device are as follows:
■ EP2AGX45 and EP2AGX65 devices contain 50 PCLKs
■ EP2AGX95 and EP2AGX125 devices contain 59 PCLKs
■ EP2AGX190 and EP2AGX260 devices contain 84 PCLKs
■ EP2AGZ225, EP2AGZ300, and EP2AGZ350 devices contain 88 PCLKs
PCLKs have higher skew when compared with the GCLK and RCLK networks. You
can use PCLKs instead of general purpose routing to drive signals into the Arria II
device.
Figure 5–5. PCLK Networks (EP2AGX45 and EP2AGX65 Devices)
Top Left PLL
CLK[12..15]
PLL_1
Top Right PLL
PLL_2
PCLK[0..8]
Q1 Q2
Q4 Q3
PCLK[9..17]
PLL_4
Bottom Left PLL
CLK[4..7]
PCLK[34..49]
PLL_5
PLL_6
Center PLLs
CLK[8..11]
PCLK[18..33]
PLL_3
Bottom Right PLL
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation