EP2AGX95EF29C6N Datasheet, PDF (117/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 5: Clock Networks and PLLs in Arria II Devices
5–9
Clock Networks in Arria II Devices
1 A spine clock is another layer of routing below the GCLKs, RCLKs, and PCLKs before
each clock is connected to the clock routing for each LAB row. The settings for spine
clocks are transparent. The Quartus II software automatically routes the spine clock
based on the GCLK, RCLK, and PCLKs.
Clock Regions
Arria II GX devices provide up to 64 distinct clock domains (16 GCLKs + 48 RCLKs)
in the entire device, while Arria II GZ devices provide up to 104 distinct clock
domains (16 GCLKs + 88 RCLKs). Use these clock resources to form the following
three types of clock regions:
■ Entire device
■ Regional
■ Dual regional
To form the entire device clock region, a source (not necessarily a clock signal) drives a
GCLK network that can be routed through the entire device. This clock region has a
higher skew when compared with other clock regions, but allows the signal to reach
every destination in the device. This is a good option for routing global reset and clear
signals or routing clocks throughout the device.
To form a regional clock region, a source drives a single-quadrant of the device. This
clock region provides the lowest skew in a quadrant and is a good option if all
destinations are in a single device quadrant.
To form a dual-regional region, a single source (a clock pin or PLL output) generates a
dual-regional clock by driving two regional clock networks (one from each quadrant).
This technique allows destinations across two device quadrants to use the same
low-skew clock. The routing of this signal on an entire side has approximately the
same delay as in a regional clock region. Internal logic can also drive a dual-regional
clock network. For Arria II GX devices, corner PLL outputs generate a dual-regional
clock network through clock multiplexers that serve the two immediate quadrants of
the device. For Arria II GZ devices, corner PLL outputs only span one quadrant, they
cannot generate a dual-regional clock network.
July 2012 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration