EP2AGX95EF29C6N Datasheet, PDF (359/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 10: SEU Mitigation in Arria II Devices
User Mode Error Detection
10–3
1 For more information about the timing requirement to shift out error information
from the EMR, refer to “Error Detection Timing” on page 10–7.
The error detection circuitry continues to calculate the CRC_ERROR and 16-bit
signatures for the next frame of data regardless of whether an error has occurred in
the current frame or not. You must monitor the CRC_ERROR signal and take the
appropriate actions if a CRC error occurs.
The error detection circuitry in Arria II devices uses a 16-bit CRC-ANSI standard
(16-bit polynomial) as the CRC generator. The computed 16-bit CRC signature for
each frame is stored in the configuration RAM. The total storage size is 16 (number of
bits per frame) × the number of frames.
The CRC_ERROR signal is asserted if the error detection circuitry verification does not
match with the configuration-computed CRC value. However, the Arria II device
error detection CRC feature does not check the memory blocks and I/O buffers.
Therefore, the CRC_ERROR signal may stay solid high or low, depending on the error
status of the previously checked configuration RAM frame. The I/O buffers are not
verified during error detection because these bits use flipflops as storage elements
that are more resistant to soft errors when compared with configuration RAM cells.
MLAB and M9K memory blocks support parity bits that are used to check the
contents of the memory blocks for any error in Arria II GX devices. In addition to
MLAB and M9K memory blocks, M144K memory blocks are used to check the
contents of the memory blocks for any error in Arria II GZ devices.
f For more information about error detection in Arria II memory blocks, refer to the
Memory Blocks in Arria II Devices chapter.
To provide testing capability of the error detection block, a JTAG instruction,
EDERROR_INJECT, is provided. This instruction is able to change the content of the
21-bit JTAG fault injection register used for error injection in Arria II devices, thereby
enabling the testing of the error detection block.
1 You can only execute the EDERROR_INJECT JTAG instruction when the device is in user
mode.
Table 10–1 lists the EDERROR_INJECT JTAG instruction for Arria II devices.
Table 10–1. EDERROR_INJECT JTAG Instruction for Arria II Devices
JTAG Instruction
EDERROR_INJECT
Instruction Code
00 0001 0101
Description
This instruction controls the 21-bit JTAG fault
injection register used for error injection.
You can create a Jam™ file (.jam) to automate the testing and verification process.
This allows you to verify the CRC functionality in-system and on-the-fly, without
having to reconfigure the device.
f For more information about .jam, refer to AN 539: Test Methodology of Error Detection
and Recovery using CRC in Altera FPGA Devices.
February 2014 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration