EP2AGX95EF29C6N Datasheet, PDF (118/380 Pages) Altera Corporation – Device Interfaces and Integration

5–10
Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Figure 5–10 and Figure 5–11 show the dual-regional clock region for Arria II devices.
Figure 5–10. Device Dual-Regional Clock Region for Arria II GX Devices
PLL_1
PLL_2
Regional clock
multiplexers
Clock pins or PLL outputs
can drive half of the device to
create side-wide clocking
regions for improved
interface timing.
PLL_4
PLL_3
Figure 5–11. Device Dual-Regional Clock Region for Arria II GZ Devices
T1 T2
Regional clock
multiplexer
L2
R2
L3
R3
B1 B2
Clock pins or PLL outputs
can drive half of the device to
create side-wide clocking
regions for improved
interface timing.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation