EP2AGX95EF29C6N Datasheet, PDF (134/380 Pages) Altera Corporation – Device Interfaces and Integration

5–26
Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
Figure 5–23. External Clock Outputs for Left and Right PLLs in Arria II GZ Devices
C0
C1
C2
Left/Right
C3
PLLs
C4
C5
C6
m(fbout)
clkena0 (3)
Internal Logic
clkena1 (3)
PLL_<L2, L3, R2, R3>_CLKOUT0n/FB_CLKOUT0p (1), (2)
PLL_<L2, L3, R2, R3>_FB_CLKOUT0p/CLKOUT0n (1), (2)
Notes to Figure 5–23:
(1) You can feed these clock output pins using any one of the C[6..0], or m counters.
(2) The CLKOUT0p and CLKOUT0n pins are dual-purpose I/O pins that you can use as two single-ended outputs or one single-ended output and
one external feedback input pin.
(3) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
Each pin of a single-ended output pair can either be in-phase or 180° out-of-phase.
The Quartus II software places the NOT gate in your design into the IOE to
implement a 180° phase with respect to the other pin in the pair. The clock output pin
pairs support the same I/O standards as standard output pins, as well as LVDS_E_3R,
LVPECL, differential high-speed transceiver logic (HSTL), and differential SSTL.
f To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the I/O Features in Arria II Devices chapter.
Arria II PLLs can also drive out to any regular I/O pin through the GCLK or RCLK
network. You can also use the external clock output pins as user I/O pins if you do
not require external PLL clocking. However, external clock output pins can support a
differential I/O standard that is only driven by a PLL.
1 Regular I/O pins cannot drive the PLL clock input pins.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation