EP2AGX95EF29C6N Datasheet, PDF (22/380 Pages) Altera Corporation – Device Interfaces and Integration

1–8
Chapter 1: Overview for the Arria II Device Family
Arria II Device Architecture
■ Diagnostic features
■ Serial loopback from the transmitter serializer to the receiver CDR for
transceiver physical coding sublayer (PCS) and PMA diagnostics
■ Parallel loopback from the transmitter PCS to the receiver PCS with built-in self
test (BIST) pattern generator and verifier
■ Reverse serial loopback pre- and post-CDR to transmitter buffer for physical
link diagnostics
■ Loopback master and slave capability in PCIe hard IP blocks
■ Support for protocol features such as MSB-to-LSB transmission in a
SONET/SDH configuration and spread-spectrum clocking in a PCIe
configuration
Table 1–5 lists common protocols and the Arria II dedicated circuitry and features for
implementing these protocols.
Table 1–5. Sample of Supported Protocols and Feature Descriptions for Arria II Devices
Supported Protocols
PCIe
XAUI/HiGig/HiGig+
GbE
CPRI/OBSAI
Feature Descriptions
■ Complete PCIe Gen1 and Gen2 protocol stack solution compliant to PCIe Base
Specification 2.0 that includes PHY/MAC, Data Link, and Transaction layer circuitry
embedded in the PCIe hard IP blocks.
■ PCIe Gen1 has x1, x2, x4, and x8 lane configurations. PCIe Gen2 has x1, x2, and x4 lane
configurations. PCIe Gen2 does not support x8 lane configurations
■ Built-in circuitry for electrical idle generation and detection, receiver detect, power state
transitions, lane reversal, and polarity inversion
■ 8B/10B encoder and decoder, receiver synchronization state machine, and ±300 parts
per million (PPM) clock compensation circuitry
■ Options to use:
■ Hard IP Data Link Layer and Transaction Layer
■ Hard IP Data Link Layer and custom Soft IP Transaction Layer
■ Compliant to IEEE P802.3ae specification
■ Embedded state machine circuitry to convert XGMII idle code groups (||I||) to and from
idle ordered sets (||A||, ||K||, ||R||) at the transmitter and receiver, respectively
■ 8B/10B encoder and decoder, receiver synchronization state machine, lane deskew, and
±100 PPM clock compensation circuitry
■ Compliant to IEEE 802.3 specification
■ Automatic idle ordered set (/I1/, /I2/) generation at the transmitter, depending on the
current running disparity
■ 8B/10B encoder and decoder, receiver synchronization state machine, and ±100 PPM
clock compensation circuitry
■ Transmit bit slipper eliminates latency uncertainty to comply with CPRI/OBSAI
specifications
■ Optimized for power and cost for remote radio heads and RF modules
1 For other protocols supported by Arria II devices, such as SONET/SDH, SDI, SATA
and SRIO, refer to the Transceiver Architecture in Arria II Devices chapter.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2012 Altera Corporation