EP2AGX95EF29C6N Datasheet, PDF (53/380 Pages) Altera Corporation – Device Interfaces and Integration

Chapter 3: Memory Blocks in Arria II Devices
3–5
Memory Features
Figure 3–2 shows how the wren and byteena signals control the operations of the
MLABs. Falling clock edges triggers the write operation in MLABs.
Figure 3–2. Byte Enable Functional Waveform for MLABs
inclock
wren
address
an
a0
a1
a2
a0
a1
a2
data
XXXX
ABCD
XXXX
byteena
XX
10
01
11
XX
contents at a0
FFFF
ABFF
contents at a1
FFFF
FFCD
contents at a2
current data: q (asynch)
doutn
FFFF
ABCD
FFFF ABFF FFFF FFCD FFFF ABCD ABFF
FFCD
FFCD
Packed Mode Support
Arria II M9K and M144K blocks support packed mode. The packed mode feature
packs two independent single-port RAMs into one memory block. The Quartus II
software automatically implements the packed mode where appropriate by placing
the physical RAM block into true dual-port mode and using the MSB of the address to
distinguish between the two logical RAMs. The size of each independent single-port
RAM must not exceed half of the target block size.
Address Clock Enable Support
Arria II memory blocks support address clock enable, which holds the previous
address value for as long as the signal is enabled (addressstall = 1). When you
configure the memory blocks in dual-port mode, each port has its own independent
address clock enable. The default value for the address clock enable signal is low
(disabled).
December 2011 Altera Corporation
Arria II Device Handbook Volume 1: Device Interfaces and Integration