EP2AGX95EF29C6N Datasheet, PDF (54/380 Pages) Altera Corporation – Device Interfaces and Integration

3–6
Chapter 3: Memory Blocks in Arria II Devices
Memory Features
Figure 3–3 shows an address clock enable block diagram. The port name
addressstall refers to the address clock enable.
Figure 3–3. Address Clock Enable
address[0]
1
address[0]
0
register
address[0]
address[N]
addressstall
1
address[N]
address[N]
0
register
clock
Figure 3–4 shows the address clock enable waveform during the read cycle.
Figure 3–4. Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
a0
a1
a2
rden
addressstall
latched address
(inside memory)
an
a0
q (synch)
doutn-1 doutn dout0
q (asynch)
doutn dout0
a3
a4
a1
dout1
dout1
a5
a6
a4
a5
dout4
dout4 dout5
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2011 Altera Corporation