EP2AGX95EF29C6N Datasheet, PDF (31/380 Pages) Altera Corporation – Device Interfaces and Integration

December 2010
AIIGX51002-2.0
AIIGX51002-2.0
2. Logic Array Blocks and Adaptive Logic
Modules in Arria II Devices
This chapter describes the features of the logic array block (LAB) in the Arria^® II core
fabric. The LAB is composed of basic building blocks known as adaptive logic
modules (ALMs) that you can configure to implement logic functions, arithmetic
functions, and register functions.
This chapter contains the following sections:
■ “Logic Array Blocks” on page 2–1
■ “Adaptive Logic Modules” on page 2–5
Logic Array Blocks
Each LAB consists of ten ALMs, various carry chains, shared arithmetic chains, LAB
control signals, local interconnect, and register chain connection lines. The local
interconnect transfers signals between ALMs in the same LAB. The direct link
interconnect allows the LAB to drive into the local interconnect of its left and right
neighbors. Register chain connections transfer the output of the ALM register to the
adjacent ALM register in the LAB. The Quartus^® II Compiler places associated logic in
the LAB or the adjacent LABs, allowing the use of local, shared arithmetic chain, and
register chain connections for performance and area efficiency.
Figure 2–1 shows the Arria II LAB structure and the LAB interconnects.
Figure 2–1. LAB Structure in Arria II Devices
C4 C12
Row Interconnects of
Variable Speed & Length
R20
R4
Direct link
interconnect from
adjacent block
ALMs
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Local Interconnect _LAB
Direct link
interconnect to
adjacent block
MLAB
Local Interconnect is Driven
from Either Side by Column Interconnect
& LABs, & from Above by Row Interconnect
Column Interconnects of
Variable Speed & Length
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Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
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